The present invention relates to a semiconductor memory device, and more particularly to a non-volatile memory device having a multi-level gate structure.
General non-volatile memory devices include storage cell transistors having a multi-level gate structure in a cell array region, and associated transistors having a single-level gate structure for operating the storage cell transistors in a peripheral circuit region. An electrically erasable programmable read only memory (EEPROM) which can be erased and reprogrammed electrically is one type of the memory devices having a multi-level gate structure. A storage cell transistor of the EEPROM has a floating gate electrode for storing data, and a control gate electrode for controlling the floating gate electrode. In the storage cell transistor, an interlayer insulating film is provided between the control gate electrode and floating gate electrode, and a tunnel oxide layer is disposed between the floating gate electrode and a substrate.
A conventional technique for such an EEPROM is disclosed by R. Shirota, et al in IEDM, 1990, pp. 103.about.106, entitled: "A 2.3 mm.sup.2 Memory Cell Structure for 16 Mb NAND EEPROMs".
FIGS. 1A to 1J show a process for manufacturing an EEPROM having a multi-level gate structure according to a known conventional technique. FIGS. 1A, 1C, 1E, 1G and 1I are longitudinally sectioned views showing a cell array region and peripheral circuit region of the EEPROM manufactured by a sequential process. FIGS. 1B, 1D, 1F, 1H and 1J are sectional views showing the peripheral circuit region laterally cut away from FIGS. 1A, 1C, 1E, 1G and 1I, respectively.
Referring to FIGS. 1A and 1B, a field oxide layer 101 is formed on a substrate 100 by a common LOCal Oxidation of Silicon (LOCOS). Then, a gate oxide layer 105 is formed on the whole surface of the substrate 100. The gate oxide layer 105 is etched by a photolithography to have a storage cell transistor in the cell array region thereon. Thereafter, a thin tunnel oxide layer 102 is formed on the surface of the substrate 100 in the portion where the storage cell transistor is formed. A first polycrystalline silicon layer 103 and an ONO (oxide/nitride/oxide) layer 104 which is an interlayer insulating film are sequentially formed thereon. Thereafter, using a photoresist pattern 106 as a mask, the layers on the peripheral circuit region only are sequentially etched by a conventional etching method, to thus expose the surfaces of the field oxide layer 101 and substrate 100. The first polycrystalline silicon layer 103 is a conductive layer for a floating gate electrode of the storage cell transistor.
Referring to FIGS. 1C and 1D, after removing the photoresist pattern 106, a gate oxide layer 107 is formed on the substrate 100 in the peripheral circuit region through a thermal oxidation, and a second polycrystalline silicon layer 108 and a tungsten silicide layer 109 are sequentially formed on the resultant surface. The second polycrystalline silicon layer 108 and tungsten silicide layer 109 form a control gate electrode of the storage cell transistor and a gate electrode of the transistor in the peripheral circuit region.
Referring to FIGS. 1E and 1F, a photoresist pattern 110 is formed on the peripheral circuit region to form the gate electrode of the transistor. The tungsten silicide layer 109 and second polycrystalline silicon layer 108 are etched to expose the surface of the field oxide layer 101 and the gate oxide layer 107. Thereafter, a ion-implantation is performed to form source and drain regions of the transistor in the peripheral circuit region as indicated in FIG. 1E.
Referring to FIGS. 1G and 1H, after removing the photoresist pattern 110, a photoresist pattern 111 is formed on the cell array region. The tungsten silicide layer 109, the second polycrystalline silicon layer 108, the ONO layer 104 and the first polycrystalline silicon layer 103 are then etched until the surface of the tunnel oxide layer 102 and the gate oxide layer 105 is exposed, thereby forming a storage cell transistor. Next, an ion-implantation is performed to form source and drain regions of the storage cell transistor.
Referring to FIGS. 1I and 1J, after removing the photoresist pattern 111, a drive-in is performed to form the source and drain regions of the transistor in the peripheral circuit region, and the source and drain regions of the storage cell transistor in the cell array region. An insulating layer of a low-temperature oxide (LTO) layer 112 and a borophosphorous silicate glass (BPSG) layer 113 are sequentially formed on the whole surface of the substrate 100, and a reflow process is performed. Finally, an opening is formed in the portions of the cell array region and the peripheral circuit region which will be contacted with metal layers 114 and 115 respectively, and then, the metal layers 114 and 115 are formed.
In a memory device having a multi-level gate structure manufactured by the conventional technique shown in FIGS. 1A to 1J, since the gate structure of the storage cell transistor 12 in the cell array region differs from that of the transistor 11 in the peripheral circuit region, additional photolithography processes are required as illustrated in FIGS. 1A, 1E and 1G. Due to this fact, the ONO layer 104 which is the interlayer insulating film is contaminated owing to an organic photoresist. Moreover, the damage on the field oxide layer resulting from numerous etching processes degrades insulating performance, and complicates the manufacturing process.